Emerging Memory Array Characterization Engineer

As an array characterization engineer focusing on Emerging Memory working at Micron Technology, Inc., you will be evaluating technologies that enable further memory scaling. A range of technologies will be targeted, such as PCM, RRAM, STTRAM, 3D, Crosspoint, FBC, etc., both for non-volatile, and volatile memories. You will be responsible for the development of memory-test patterns, analyzing electrical failures, improvement of yield and of overall cell performance, debug, design, simulation and implementation of circuit and process changes on test chips.  Additionally, you will work with Design, Process, and Manufacturing departments to enable learning on new cell technologies, ranging from single cell structures through test chip arrays.



  • Analyze array reliability and support process qualification of emerging memory technologies to enable new product development and manufacturability.
    • Understand array reliability failure modes, the underlying physical mechanisms, and test methods for accelerating those mechanisms.
    • Perform statistical analysis of array data collected across a variety of test platforms, including single die, wafer level, and lot level.
    • Collaborate with test engineers to enable volume data collection at wafer and unit level.
    • Utilize engineering test stations to design, implement and analyze array characterization experiments.
  • Develop testmodes to enable reliability and array characterization on process development vehicles and production devices.
    • Work with design and test engineers to propose, refine, and validate design features that enable cost effective array characterization (design for test).
    • Correlate array reliability and characterization testing to product reliability.
  • Perform and analyze array characterization of memory elements and devices.
    • Gain understanding of array architecture and circuits, as well as cell properties, functionality, and reliability through cross functional interaction.
    • Devise and execute experiments to evaluate memory cell capabilities and properties and the effects on reliability, functionality, and performance.
    • Develop test system software and hardware as necessary to perform functions above.
  • Develop and support test chips, gather and disseminate data related to array device physics.
    • Work with design and process integration engineers to provide requirements and validate functionality of test chips to explore array device physics.
    • Perform tests and propose testing solutions to generate data corresponding to array device physics.
    • Analyze data and provide feedback to process integration and design to enable process and design improvements.
  • Define, support and gather data on media management techniques, on-chip and in-system to improve performance and reliability of end product.
    • Support analysis of existing systems, using knowledge of design, device, and reliability to propose exploration paths.
    • Distill system knowledge and device knowledge into proposals for memory management features.
    • Support media management exploration with experiments and data analysis to validate assumptions and virtually qualify media management techniques.
    • Support generation of RSG and system level verification of media management techniques.
  • General data analysis
    • Work to pull data together from required data sources (probe, param, fab, bench, etc), analyze and compile conclusions.
    • Present data in a clear and concise format, using appropriate plot/method to best convey conclusions.


For this position it is essential you have excellent problem-solving and analytical skills as well as good communication, organizational, and team building skills.  The ability to work in teams and to work well with others and to be a self-starter with strong work ethic is also critical for this job.



Successful candidate for this position will have:

  • Thorough understanding of mainstream memory technologies such as DRAM, NAND, NOR, & SRAM acquired through significant industry experience
  • Familiarity with Circuit/Architecture issues facing Memory Cell performance
  • Proficiency with data analysis, DOE, and statistical techniques
  • Must be willing to work weekends or evenings, if necessary



An MS degree or equivalent foreign education in Electrical, Electronics Engineering or a BS degree or equivalent foreign education in Electrical, Electronics Engineering with five years’ progressive post-baccalaureate experience




Keywords: Boise || Idaho (US-ID) || United States (US) || Technology Development || Experienced || Regular || Engineering || #LI-MT1 ||

Full time
Boise, Idaho 83701, US