DFT Engineers / DFT Lead


Experience : 4 – 15+ years

Looking for bright ASIC design engineer with excellent analytical and technical skills. This role provides opportunity to participate in the ASIC development, with emphasis in DFT, coverage, timing closure and post-silicon diagnosis,
Roles and Responsibilities
- Experience in architecting DFT - top level test pin planning, ATPG partitioning, MBIST planning and optimization, JTAG TDR planning and integration, architecting DFT clocking schemes, EFUSE planning for memory repair
- Defining scan compression, low coverage analysis, improve test coverage for various fault models, pattern generation, simulation with SDF
- Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies
- Executed scan & MBIST insertion, ATPG and verification at full chip level
- Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts
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- Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations)
- Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification
- Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests
- Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved
- Understanding of Power Estimation/Management for DFT modes is preferred
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- Strong written and oral communication skills
- Good understanding of Deep Sub Micron topics and their associated issues
Posted
07/25/2022
Location
Bengaluru, KA, IN