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Staff Design Engineer- RTL, MicroArchitecture

Location: Hyderabad

  • Staff Design Engineer- RTL, MicroArchitecture

We new-generation computing unleashing the potential of AI to enable leaps in the value technology delivers to improve the way we all work and live. We offer transformative edge computing solutions for AI data collection and processing at the edge of network, with a focus on smart vision applications including automobility, retail, security, industrial, and metro. We are funded by strategic and venture investors DENSO, Daimler, SPARX Group, Magna, Samsung Catalyst Fund, Temasek, GGV Capital, Wavemaker, and SGInnovate. With headquarters in El Dorado Hills (CA), We have

teams in Campbell (CA), Cary (NC), and subsidiaries in Hyderabad (India), Manila (Philippines), and Leeds and Kings Langley (UK), with 300+ employees worldwide.

Roles and Responsibilities

We work on complex high performance, fully programmable, low power design of Graph Streaming Processor, an architecture specially designed for machine learning/visual applications. As a member of our focused group of HW engineering, the candidate will be involved in designing a stream processor and memory subsystem working on every aspect of hardware design and will be involved in close interactions with both SDK and backend teams for performance tuning, area, and power optimizations of multi million gate design.


  • BE/BTech/ME/MTech in Computer Science or Electronics or Electrical
  • 8+ years of experience


  • Capability to understand a given block specification and come up with Micro Architecture
  • Capability to derive an architecture and micro architecture based on a given algorithm
  • Experience in processor design – RISC/DSP/VLIW/SIMD architectures and/or memory subsystem design, cache hierarchy design.
  • Knowledge in digital logic for HW safety/protection – ECC, Parity, WDT etc.
  • Experience of multi-million gate ASIC design and verification methodologies
  • Knowledge of Computer architecture
  • Experience in AMBA AXI, AHB, and APB protocols
  • Expertise in System on Chips.
  • Knowledge of digital design methodologies and tool flow
  • Excellent logic design, debugging and problem-solving skills.
  • Experience in logic design with Verilog and/or System Verilog and validation/verification
  • Experience in lint checks, area optimization, power optimization, GLS, synthesis and timing analysis
  • Experience in Multi-clock domain, Interconnects
  • Knowledge on Memory subsystem


  • Knowledge in Automotive ISO 26262 Functional Safety Standard is a plus.
  • Experience with DSP, Datapath design and floating-point math a plus
  • Knowledge of SIMD, MIMD, VLIW, and parallel processing a plus
  • Understanding of GPU/AI/ML Processor architecture

Contact: Uday Bhaskar

Mulya Technologies

"Mining the Knowledge Community"

Email id :

hyderabad, TG, IN