Who are we and what do we do?
Isolation (ISO) team works on different product families involving High Voltage Isolation (~kV rms & DC) of signal & power. Isolation is a means of preventing DC and unwanted AC currents between two parts of a system, while allowing signal and power transfer between those two parts. The team works very closely with ATD, SCP, TTG & Kilby Labs due to the technology development oriented nature of the products. It is one of the fastest growing Product Lines in TI in terms of revenue. The products cater to mostly Industrial & Automotive markets.
What will you be doing in this role?
Develop and execute detailed pre-silicon Verification plans working closely with Systems and Applications team and Analog and Digital design teams
Develop SystemVerilog chip-level test-cases and behavioral models for analog blocks based on the verification plan
Run an automated / regression based DV suite and extract key measurements based on automatic extractors and populate them on Starfish
Work closely with design and systems teams to review / close spec gaps and design bugs, as they arise
Implement AMS TBs in Cadence Virtuoso and / or Verilog-AMS to apply stimulus and check for pass/fail criteria
Drive new and improved methodologies where needed, work with the EDA team to upgrade DV tools and flows
Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tape-out
Participate in design reviews and create necessary design verification and product documentation
Work with test engineers / designers to come up with optimized DFT techniques and execute pre-silicon verification of mixed-signal products
What do we expect from you?
Knowledge and Skills
Good grasp of analog design and digital design fundamentals and be able to apply this knowledge to the full chip verification of a mixed signal IC
Understanding of basic analog building blocks and mixed signal blocks.
Experience in usage of Cadence Virtuoso tool set and SystemVerilog for Design Verification.
Strong hands-on working experience in Analog / digital verification for Mixed-signal chips
Prior Industry experience in Mixed signal/Analog SoC Design Verification
Ability to write an exhaustive chip level verification plan from the specs
Experience with implementation of modern verification environments that include constrained random stimulus and use of functional coverage
Expert in using simulation tools (preferably ncsim)
Bachelors / Masters in Electrical / Electronics Engineering
Other
Good team player, attitude and thirst for continuous learning
Strong communication and interpersonal skills
Ability to function independently, be self-driven
Preferred Skills/ Experience
3-8 years of relevant experience
DV Exposure to protocol-based systems like USB
Strong hands-on working experience in Analog / digital verification for Mixed-signal chips
Good in verification approach, flow, concepts and excellent debugging skills
Exposure to any other HVLs (System Verilog, VerilogAMS) as a developer / user.
Experience in metric based Verification closure using Code and Functional coverage
Expertise in automation using Perl / Tcl / shell scripting