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Soc DFT Engineer


Job Description
Strong knowledge of DFT architectures and methodologies which includes Scan, ATPG, MBIST, BSCAN, TAP, JTAG, etc and proven knowledge of Verilog and System Verilog, RTL design and micro-architecture skills. Strong knowledge of SoC tools, methodology ( VCS, Synthesis, Spyglass, Tessent Industry standard ATPG/MBIST tools design compiler etc. and also DFT design on Physical design highly desirable). In addition, this position requires interaction and fulfilling the requirements of Intel's post-silicon/ATE teams, Silicon Debug and understanding HVM (High Volume Manufacturing) requirements. Strong debug skills and demonstrated experiences in Perl and TCL scripting are a must. Strong Communications skills and the ability to effectively work with cross functional teams across geographies are required. We are looking for smart and enthusiastic Engineers to develop Design For Testability for our SOCs.
Qualifications
B.Tech or M.Tech with minimum of 8 years of experience in DFT domain. Excellent scripting (PERL, Python) and debug analytic skills. Deep technical knowledge of DFT architecture design methodologies and CAD tools - SCAN, ATPG, JTAG, BSCAN and MBIST.Experience with design integration process.Pre/Post Si DFx hands-on experience (insertion, verification, coverage, debug) including production test vector generationInside this Business Group
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
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Company
Intel
Posted
06/23/2022
Location
bangalore, KA, IN