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Digital Verification Communication Subsystems (f/m/div)*

Are you able to collaborate across boundaries and coordinate between various stakeholders? Do you bring a pioneering spirit as well as experience with digital verification methodologies and tools? Then take the chance and come on board! We have several open opportunities for you as Digital Verification Engineer depending on the experience you bring along! Joining us you will be part of an international team, working in close cooperation with our design teams to achieve verification goals, thus ensuring design and execution quality.Responsibilities
As a Digital Verification Engineer, you will support the development of Capacitive Sensing IP, Audio IP, Automotive Peripheral IP and CPU Subsystems. You will be part of a dynamic and experienced team and take their technical knowledge to the next level in our mission of excellence.
In your new role you will:
Be responsible for the verification of digital designs for CPU Subsystems, Communication Subsystems, Capacitive Sensing IP, and Audio IP;
Be able to understand requirements & specifications;
Focus on Test plan and test bench development;
Be responsible for IP verification (Formal, SystemVerilog, UVM);
Support the Flow & Methodology improvements.
Your Profile
You have a structured work style and demonstrate high-quality standards for yourself and other people. As a true team player, you set the direction in your field of expertise and cooperate across boundaries by recognizing and using different areas of expertise and skills of the team members. You enjoy developing your knowledge and skills and motivate yourself and others to achieve top performance. Furthermore, you demonstrate strong communication skills and know-how to establish lasting relationships and networks.
You are best equipped for this role if you have:

A Degree in Electronic or Computer Engineering;
2 to 10+ years of industry experience in digital verification (we have multiple roles available);
Development of verification environments and methodologies at block and subsystem level;
Extensive knowledge of SystemVerilog / Verilog / OVM / UVM / VMM;
Fluency in English.
Benefits:
Coaching, mentoring networking possibilities
Wide range of training offers & planning of career development
Different career paths: Technical Ladder, Management & Individual Contributor
Flexible working conditions
Medical coverage
Health promotion programs
On-site Kitchen available
Company Sick Paid Leave Scheme
Company Pension Scheme
Annual Success Bonus Scheme
Monthly Commuter Ticket fully expensed by Company
Accessibility, access for wheelchairs
Posted
04/25/2022
Location
Dublin, Dublin, IE