Circuit Layout Designer

Requisition ID: 21401  The Quantum Information and Integrated Nanosystems Group conducts quantum information science research from a shared foundation of innovative control-signal design, outstanding fabrication tools, and well-equipped measurement laboratories. The group has a broad range of experimental and prototyping activities. The group's quantum information science activities include the development of superconducting and trapped-ion qubits and quantum sensing with nitrogen-vacancy (NV) centers in diamond. In addition, the group has robust capabilities in classical superconducting circuits, complementary metal-oxide semiconductor (CMOS) design and fabrication, and integrated photonics. These component technologies are used in synergy with quantum information science demonstrations, as well as in standalone applications that include beyond-CMOS circuit technologies, energy-starved sensors, compact optical communication and laser radar transceivers, and microwave photonic signal processing.

The Group is seeking a Circuit Layout Designer, specializing in mixed-signal IC layout and mask design engineering for in-house and foundry-available CMOS processes as well as emerging integrated circuit technologies. The Circuit Layout Designer will work with the IC design team to take circuit designs from schematic through physical verification, tape-out, and/or reticle assembly. Ability to perform layout at all levels of hierarchy is required, from leaf cell to top-level floor-planning and chip assembly. The successful candidate will have a solid understanding of CMOS and the ability and desire to learn silicon photonic and superconducting electronics technologies.

  • A Bachelor’s degree in electrical or electronics engineering or a related engineering discipline with a focus on integrated circuit (IC) computer-aided design (CAD), plus 3 years’ experience is required. An Associate’s Degree in computer-aided design (CAD) or a related engineering discipline, or relevant experience of at least 7 years will also be considered.
  • Comprehensive understanding of layout flows, methodologies and layout of digital and analog blocks for use in larger mixed-signal circuits.
  • Strong written and verbal communication skills and ability to define and adhere to project layout schedules is required.
  • Experience managing design tools and the related infrastructure required for IC design and layout. 
  • Experience with automatic placement and routing tools, schematic and layout tools such as Cadence Virtuoso, and Mentor Calibre for design creation and verification, is strongly desired.
  • Experience with revision control software, SKILL scripting, minor process design kit (PDK) modification to support layout flows, and experience with chip-level floor-planning, are strongly preferred.

MIT Lincoln Laboratory is an Equal Employment Opportunity (EEO) employer. All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, veteran status, disability status, or genetic information; U.S. citizenship is required.

MIT Lincoln Laboratory
Full time