Digital Design Engineer

Digital Design Engineer

Synopsys Inc | Bangalore, KA, IN

Posted a month ago

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Description

Job description as below:


At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.


Our Silicon IP Subsystems business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.


ASIC Digital Design Engineer, Senior

Here we go, look for more information on Interface IP Subsystems @ https://www.synopsys.com/designware-ip/ip-subsystems.html


We’re looking for a Senior ASIC Digital Design Engineer / Verification Engineer to join the team.

Come and be part of a collaborative team environment that innovates and develops the latest DesignWare IP Subsystem solutions that enable the way the world designs. Join the Synopsys Subsystems Team !


Based in our offices in Bangalore, India, you will be a senior member of the Synopsys Solutions Group Subsystems team, which is developing high performance interface IP Subsystem solutions for DDR, PCIe, Ethernet and other interface protocols.


In this role,


  • As a Lead Design Engineer, you will be responsible for RTL Design, Integrating the Subsystems, signing off on the front-end implementation flows, working with Design and Verification teams driving the life-cycle of the Subsystems.


  • As a Lead Verification Engineer, you will be responsible for signing off on Subsystems Verification, working closely with the Design leads, from test plan, test environment to sign-off, driving the life-cycle of the Subsystems.


Requirements :


--- Knowledge of one or more of protocols AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols.

--- Programming skills such as System Verilog, TCL, Perl or Python.

--- The ability to work independently, precisely and to drive innovation

--- The ability to extract detailed requirements from high-level specification

--- Good communication skills.


Lead Design Engineer position will require you to:


-- Understand the requirements and Architect the Subsystems based on the requirements.

-- Integrate the RTL and drive the Design tasks to build the Subsystem

-- Sign-off on the front-end implementation flows.

-- Be part, and, lead the Verification closure by interacting with the Verification teams

-- Drive the life-cycle of the Subsystems through various phases, from requirements to delivery.


Key Qualifications for Design Engineers:


  • ** Hands-on/Lead experience on Subsystems/SOC Design, Architecture and Implementation.
  • ** Experience with Verilog/System Verilog coding and simulation tools
  • ** Experience of implementation flows, namely: synthesis flow, lint, CDC, low power and others


Verification Lead Engineer position will require you to:


-- Understand the Subsystem requirements/specification and author the Verification Plan

-- Bring up the SV UVM Test Environment, by coordinating with the Verification team

-- Drive the Verification closure of Subsystems with quality metrics.

-- Closely work with Design Leads and own/drive the verification signoff.


Key Qualifications for Verification Engineers


  • ** Hands-on/Lead experience on Subsystem Verification.
  • ** Verification experience and debug skills of IP cores and/or Subsystems and/or SOC RTL designs
  • ** Experience in developing System Verilog, UVM or similar HDL based test environments
  • ** Experience in developing and implementing test plans, extracting verification metrics, developing BFMs and similar verification components
  • ** Obsession with quality and finding bugs


Please get in touch with us at spooja@synopsys.com

Looking forward to talk to you !!


Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.