Design Verification Engineer

Design Verification Engineer

UST | Bangalore, KA, IN

Posted a month ago

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Description

Job Description:

  • Hands on experience on with tools VCS/IES,
  • Have Good UVM knowledge
  • Worked on Functional/Code Coverage
  • Good Digital/Verilog fundamentals
  • Experience with 4+ years
  • Good to have Serdes/DDR prior experience