Digital Verification Engineer (m/f/div)*
Are you able to collaborate across boundaries and coordinate between various stakeholders? Do you bring a pioneering spirit as well as experience with digital verification methodologies and tools? Then take the chance and come on board! We have several open opportunities for you as Digital Verification Engineer! Joining us you will be part of an international team, working in close cooperation with our design teams to achieve verification goals, thus ensuring design and execution quality.Responsibilities
As a Digital Verification Engineer you will be a key part of the verification of digital IPs that drive and support HMI and Programmable System on Chip (PSoC ) devices. You will be part of a dynamic and experienced team and your technical knowledge will lead us to the next level in our mission of excellence.
In This Role, You Will
Be responsible for the verification of digital designs that drive and support mixed signal Capacitive Sensing IP & Subsystems;
Be able to understand requirements & specifications;
Testbench Architecture & Development (UVM);
Be responsible for IP verification (Formal, SystemVerilog, UVM);
Support the Flow & Methodology improvements;
Review board participation.
The successful candidate will also be expected to lead a team of verification engineers to accomplish these goals
You are best equipped for this role if you have:
Bachelor/Masters/PhD Degree in Electrical or Computer Engineering or similar field with a focus on electronics;
7+ years industry experience;
Development of verification environments and methodologies at block and subsystem level;
Extensive knowledge of SystemVerilog / Verilog / OVM / UVM / VMM;
A willingness to learn new methodologies and to teach and develop junior engineers.