What You Will Do:
At Allegro Microsystems we architect, design and deploy advanced technology mixed signal power devices. We currently have an opening for senior level digital verification design engineer to join our expanding team in Milan (Italy), Manchester, NH (US), Buenos Aires, Argentina (S.America), and Edinburgh, Scotland (UK). This opportunity will allow an individual to contribute within the framework of a broader experienced analog, mixed-signal and digital team. We are looking for a motivated candidate that can leverage the group's experience to begin quickly contributing to the success of the team.
The primary focus for the individual will be using cutting edge tools to verify state of the art products in Allegro's Model Based Design flow for digital signal processing applications. Knowledge of Universal Verification Methodology, SystemVerilog assertions and Cadence verification tools is the key knowhow. As a member of product development team, you will also be exposed to variety of tools including MathWorks Simulink, embedded microprocessor coding, MATLAB scripting and Jama Requirements Management.
Typical tasks for a sr. Digital Design Verification engineer include:
* Preparation of digital design test plan from requirements using Cadence-vManager/vPlanner
* Definition and creation of UVM-SV test environment, test plans, tests and functional coverage
* Verification of signal processing and control algorithms using Cadence and MathWorks tools
* Analysis of test results, improving test coverage and debug of unexpected design behavior
* Running and maintenance of regression runs
* Preparation and/or leading of verification reviews
* Modification and/or debug of Simulink models in mixed signal test environment
* Coordination of verification activities with abroad team members
* Cooperation with System Engineering team on Jama Requirements
Education and Experience Requirements
The successful candidate will possess a Bachelor's / Master's degree of 5+ / 3+ years of experience in Digital Design and/or Verification. Excellent communication, documentation, problem-solving and analytical skills are required. Knowledge of SystemVerilog and UVM is a must. Experience with the usage of Jama, MATLAB/Simulink, Python is a strong plus.