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Integrated Circuit Designer


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Group 89—Quantum Information and Integrated Nanosystems Group
The Quantum Information and Integrated Nanosystems Group conducts quantum information science research from a foundation of multiple diverse fabrication technologies. These include superconducting and trapped-ion qubits, classical superconducting circuits, complementary metal-oxide semiconductor (CMOS), and integrated photonics. These component technologies are used in synergy with quantum information science demonstrations.

Group 89—Quantum Information and Integrated Nanosystems Group
The Quantum Information and Integrated Nanosystems Group conducts quantum information science research from a foundation of multiple diverse fabrication technologies. These include superconducting and trapped-ion qubits, classical superconducting circuits, complementary metal-oxide semiconductor (CMOS), and integrated photonics. These component technologies are used in synergy with quantum information science demonstrations.
This position is for an integrated circuit designer working with our CMOS process technology.  The candidate will develop foundry IP offerings (for example, standard cell libraries, memory IP, I/O libraries) and/or test circuits to be used for process monitoring and/or process performance demonstration vehicles.  Test circuit design will also include bring-up of first silicon using any or all of automatic test equipment (ATEs), printed circuit boards (PCBs) and FPGAs.  The candidate will work with multiple engineers having a variety of technical backgrounds in order to ensure a high quality of result and that design goals are met.  
The ideal candidate will have a bachelor’s degree in electrical engineering or a related field, 0-2 years of professional experience in integrated circuit design, and have completed coursework and/or gained professional experience in any of the integrated circuit design and test steps listed below:

    Custom layout of integrated circuits (Cadence Virtuoso preferred)
Modeling at the register transfer level (RTL) in Verilog or VHDL (Verilog preferred)
    Design of HDL simulation testbenches for functional verification
    Synthesis using industry-standard EDA tools (RTL Compiler or Design Compiler)
    Automatic place and route (Innovus preferred)
    Physical verification – LVS and DRC (Calibre preferred)
    Standard cell library characterization (Liberate preferred)
    Printed circuit board (PCB) schematic capture and layout
    Field programmable gate array (FPGA) design for use in benchtop testing
    Development of test vectors for automatic test equipment (ATEs)
    Use of oscilloscopes, logic analyzers, etc.
Familiarity with industry electronic design automation software, especially Cadence Virtuoso and Mentor Graphics Calibre, is desired but not required.  The ability to work and communicate effectively in an interdisciplinary environment is a must.

 

Requisition ID: 25446

For Benefits Information, click http://hrweb.mit.edu/benefits

MIT Lincoln Laboratory is an Equal Employment Opportunity (EEO) employer. All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, veteran status, disability status, or genetic information; U.S. citizenship is required.

Company
MIT Lincoln Laboratory
Posted
09/19/2018
Type
Full time
Location
MA, US